The present invention relates to an art to effectuate optimal layout of power source wirings of semiconductor devices produced in a master slice semiconductor integrated circuit development system.
The master slice system is used for producing a custom-made Large Scale Integrated Circuit Chip (LSI) LSI in a short delivery time. According to this system, a plurality of basic cells are regularly arranged on a semiconductor substrate in advance. The basic cells are then interconnected with signal wirings to implement the desired logic and produce an LSI that meets the user's requirements.
In IC devices having a multilayer structure such as those produced in the master slice system, power supplied from outside the IC is distributed throughout the IC device through a pair of power source wirings. One of the pair of power V.sub.cc source wirings a is supplied with high level voltage through an external power source device terminal and the other is supplied through an external power source terminal with a low level V.sub.ss.
Bonding pads are disposed at the peripheral portion of the semiconductor integrated circuit device's bonding pads are disposed for electrically connecting the devices logic circuits to outside devices through I/O cells. The I/O cells can selectively serve as input/output buffer circuits, output buffer circuits, input buffer circuits, and input/output buffer circuits. Above the I/O cells, on another wiring layer, a pair of power source wirings are formed. This pair of power source wirings, place over the I/O cells around peripheral portion of the IC, is termed as the "power source line".
In the interior region (cell region) of the IC, surrounded by the I/O cells, a plurality of basic cells are formed in a regular layout arrangement. In a wiring layer on the first layer above the basic cell array, are formed power source wirings for supplying power to each basic cell. This power source wiring for supplying power to the basic cell is termed as "cell power source wiring".
An example of a master slice system is described in the ISSCC DIGEST OF THE TECHNICAL PAPERS, PP. 78-79, February, 1986.
In semiconductor IC's produced by a master slice system, the number of gates per unit area is tending to increase. This increased gate density requires a proportional increase in gate power source current density within the basic cell array. To accommodate this requirement for the semiconductor IC's produced in the master slice system, it is the practice to place power source wirings over the peripheral portion of the basic cell array and place auxiliary power source wirings over the interior of the basic cell array.
The auxiliary power source wirings, by moderating current density, tend to reduce the adverse effect of electro-migration and thereby improve the electric reliability of the semiconductor IC. An example of the art to place such auxiliary power source wirings is disclosed in Japanese Laid-open Patent Publication No. 63-152163.
The present inventor has found that the following problems occur in semiconductor IC's produced in the above described master slice system:
Aluminum (AI) has been the wiring material of choice for the integrated circuits formed on a semiconductor or substrate, because it is adhesive to the silicon oxide film and easily workable. However, as the wiring becomes finer due to the increase in the packaging density of integrated circuits, the adverse effect of electro-migration has become so significant that it has become a frequent cause of breakage in the aluminum wiring. The electro-migration is a phenomenon by which the material of the wiring becomes mobile after exchanging momentum with the carriers. As a result of high current density in the wiring the phenomenon becomes more active. Hereinafter, the breakage of a wiring due to the electro-migration is referred to as "EMD" (electro-migration damage).
Further, in the semiconductor IC produced in the master slice system, power from outside the IC is supplied to the cell region through the power source lines formed over the peripheral portion of the IC's substrate. Therefore the current density in the power source lines at the peripheral portion becomes high. Therefore, measures must be taken to prevent EMD of such power source lines. One means is to improve the EMD resistance of the power source line is to widen the power source line so as to decrease the current density. However, as power source lines are widened their area increases. Therefore, in order to achieve high gate density in the semiconductor IC, the width of the power source line cannot be enlarged beyond a certain limit.
The I/O cell of the IC device produced by the master slice system may be constructed of a complementary MISFET (Metal-Insulator-Semiconductor-Field-Effect-Transistor) having a high driving capacity. Power to the I/O cell is supplied from the power source line. When the I/O cells perform switching operations to supply high voltage V.sub.cc to the cell region, currents for driving the capacitive load of cell region elements and the signal wiring capacitance are supplied to the I/O cells from the power source lines. Furthermore, when a number of I/O cells simultaneously make switching operations, a large amount of current is required through the power source lines. However because of the limited current carrying capacity of the power source lines, the voltage potential of the power source lines drops temporarily, which is not desirable. Also, when the I/O cells perform switching operations to supply interior cells with low level signals, corresponding to the ground potential V.sub.ss, charges stored in the capacitive load flow into the ground potential V.sub.ss power source lines through the I/O cells. When these operations are simultaneously performed by a large number of I/O cells, a large amount of current is caused to flow through the power source lines. However, since there is a limit in their current pulling capacity, the potential of the V.sub.ss power source lines rises temporarily, which is also undesirable. Furthermore, there is an instant in the course of the switching operation in which both the n-channel MISFET and the p-channel MISFET are simultaneously turned on. In this instant, a through-current flows from the V.sub.cc power source line to the power source line supplying the ground potential V.sub.ss. When a large number of I/O cells make simultaneous switching operations, a very large amount of through-current flows for that instant, thereby causing undesired changes in both the power source voltage V.sub.cc and ground potential V.sub.ss.
Such transient changes in potential of the power source lines result in power source noises. This noise has risk of causing malfunctions in the transistors that constitute the logic circuits. For example, when the potential of a V.sub.ss power source line to an n-channel MISFET is undesirably raised by this transient noise the source voltage of that n-channel MISFET is raised and the potential difference between its gate electrode and its source electrode is relatively lowered. A result is that when the n-channel MISFET should be in on state, it may instead be temporarily turned off or have its conductance lowered. An analogous malfunction can occur with the p-channel MISFET supplied with the power source voltage V.sub.cc.
The auxiliary power source wirings over an IC device in the master slice system are formed side by side in the same wiring layer. When the auxiliary power source wirings are formed in a lattice, the auxiliary power source wirings at the crossing point must be three-dimensionally arranged using two wiring layers to prevent occurrence of short-circuiting therebetween. Also at the positions where the auxiliary power source wirings connect to the power source lines formed at the peripheral portion, three dimensional arrangements must be made to avoid short-circuiting. This complicates the design and increases the time for developing the IC device that is produced in the master slice system.